1. Field of Invention
The present invention relates to a method for generating a clock and the circuit. More particularly, the present invention relates to a method for generating multiple clocks and the circuit.
2. Description of Related Art
Most of the integrated circuits in operations need at least one clock for synchronously controlling the several operations. Therefore, at least a main clock and the other subclock generated by the main clock are needed in use. In addition, multiple clocks are usually generated for general applications in different purposes or different operations. In the integrated circuit, for a processing system, the different clock has different individual period. For the commands in a processing system, when any one of the commands is executed, it has the option by taking several different clock or a combination of these clocks. The rising time for the clock basically is the shorter the better. However, it also needs the sufficient period to allow all of the operation commands to be complete. For example, some operations need to be complete in one clock period. Thus, it is often necessary to duplicate the clock and add together, so as to obtain the intended multiple clocks.
Conventionally, the issue usually occurred in the integrated circuit is at the rising edge or the falling edge, at which the voltage is instantly brought up or down, inducing and causing the electromagnetic interference (EMI). The EMI would affect the operation in the integrated circuit. For example, in the circuit of complementary metal-oxide semiconductor (CMOS), the transient leakage current occurs. The transient leakage current, with respect to the device of the integrated circuit, would be a large source in causing EMI.
Referring to FIG. 1, it is a drawing, schematically illustrating a conventional circuit for generating clock. A spread spectrum device 100 is connected with multiple subclock devices 102. Wherein, each of the subclock device is a circuit having a buffer 104 connected with multiple flip-flop units 106. As a result, a basic clock src_clk can be used to synchronously generate multiple subclocks.
Referring to FIG. 2A, it is a drawing, schematically illustrating a conventional clock timing chart with falling-edge trigger. It includes a main clock, a first subclock, a second subclock, a command clock, and a confirmation clock. According to any one of the main clock, the first subclock and the second subclock, the command clock is generated. A command of the command clock is received at the falling edge of the first subclock for triggering the confirmation clock. A confirmation signal of the confirmation clock is received at the just next rising-edge trigger of the second subclock after the command clock is issued.
Referring to FIG. 2B, it is a drawing, schematically illustrating a conventional clock timing chart with rising-edge trigger. It includes a main clock, a first subclock, a second subclock, a command clock, and a confirmation clock. According to any one of the main clock, the first subclock and the second subclock, the command clock is generated. A command of the command clock is received at the rising edge of the first subclock for triggering the confirmation clock. A confirmation signal of the confirmation clock is received at the just next rising-edge trigger of the second subclock after the command clock is issued.
FIG. 3 is a drawing, schematically illustrating leakage current at the edge of a pulse signal. Referring to FIG. 3, for the manners of the falling-edge trigger or the rising-edge trigger in clock as shown in FIG. 2A or FIG. 2B, the disadvantage is that when multiple subclocks are synchronous generated, the pulse edge of the clock in synchronous rising or falling would induce a leakage current. In addition, after accumulation of all of the leakage current caused by the subclocks, it causes a tremendous amount of EMI. This EMI also causes a skew on the pulse edges for the clocks that are originally synchronous.
In order to solve the foregoing issues, a digital spread spectrum clock generator has been developed in the conventional design. This clock generator can reduce the EMI effect by dispersing the EMI effect in the frequency domain. However, in this method, it needs an oscillating frequency for the necessary dispersing and therefore causes the clock frequency in the system to be random, resulting in the more complicate control on the clock. Thus, it is strongly needed to have a method for generating clock with reduced EMI and a circuit for performing the method.